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| ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ?d n b y 2 : 6 1 8w0x
y 0kt ) b e d * ?? 9? j& h } 2 4 1 n t q t"mg h n b y 2 : 6 1 8| y r? - {j 1 / 5 w? 2 / 5 w w q|r? a y ?1 *??? qr s g j g2 ?r? ? ]ur? ? ?r? 5 1 1 n i {2?|r?? h *? n b y 2 : 6 1 8 ???j|??v ;?8 ] |? ) [ j g * [ w |? ) j g *|g; g j o > 8 1 n i { g d m l > 2 4 1 n i { ?o g ) t o s *? 5 : / 9 e c g t?o?2?? *? ) t g e s *? 7 : e c d n b y 2 : 6 1 8 ?+? 2 / 9 w??%j] 6??1 ? - ?+? 3 / 6 w? 4 / 4 w?1 ) b w e e *k rq? ? +? 2 / 9 w? 4 / 6 w? a?? ) p w e e * w b w e e > 2 / 9 w ? 0x y ? 5 ? r ?? 8 5 n x ? ?? w?| ? rj n b y 2 : 6 1 8? ? y+ ? r - ]? 2 n xw ? y+ ? r ?? 3 2 n x 0 - 4#r { > 7 - @ ?# ? ? [ ?? %j -2 > r?[ m?? r y+k ? ?+ [ ? j?k ?r gw 5@r#rk ? 0?? d n p t?3 -2 |??] 5 ?@r d n p t# n b y 2 : 6 1 8gc?a 8 n n y 8 n n 5 9[ mo r g o v ? ?+? . 5 1 d? , 9 6 d k1 t *? [ m ? 0?| 2 1? 7 6 n t q t 2 1 1 n t q t2 2 4 1 n t q t? -? j0l n b y 2 : 6 2 6 n b y 2 : 6 2 72 n b y 2 : 6 2 8k ? t ?[ m ? 0? | 9? 7 6 n t q t [ 2 1 1 n t q t?-? j 0l n b y 2 : 6 1 6 [ n b y 2 : 6 1 7k ?t ? ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` b j g [ ?r0gt j x ?6 ???f {c ? [?5 #q+%- [? ? rk ?g k ?? ^ ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` v ? ?+? ?? ?? ? r ) 2 4 1 n t q t 8 5 n x 00x * ? 2 / 9 w t 3 / 6 w? 4 / 4 w y ??1 ? ?j|??v 8 1 n i { t o s? 5 : / 9 e c g t 8 1 n i { t g e s? 7 : e c d ? 0 - t q j u n { ># ? - ? [ ?? ? -? |k ?# )w 5 d n p t t] 5 ? d n p t * ? e d m lr [ - k ?r? < ? ? k { > ? w q|r? a y?1 *? ) 1 / 5 w? 2 / 5 w * ? qr y r? ) ? ! 9 6 1 n i { * ? ] t? j y r? ? ] t? j ?r? ? 2 j? ) e j w 2 * 3 j? ) e j w 3 *2 5 j? ) e j w 5 * ? y+ ? ??w i ? ? i2 ?$ ??rk ? ?+ ? "?, ) e p s * ? d n p tr] {?2 ) - * ? ?? - (6 ) -?? * ? k ?r?b y? ? c?a 8 n n ! y ! 8 n n 5 9[ mo r g o v?r? a fd n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d ________________________________________________________________ maxim integrated products 1 ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ? g? 19-4311; rev 1; 9/10 part temp range pin-package max19507etm+ -40c to +85c 48 tqfn-ep* , -,? ) q c * 0 o ] s p i t*e| v? * f q ! > ! a fd [ m|??k ?t ?|" ? t q j5 n p u p s p m b - ! j o d /|* ta5^ak ?t ?|iaa| -@? !i?|yei tg?? ?[i???4|? |l ^at ? ? % ? ? g?? e n b y j n?>i|f? 2 1 9 1 1 ! 9 6 3 ! 2 3 5 : ! )?| *l * 2 1 9 1 1 ! 2 6 3 ! 2 3 5 : ! ) | *l * t 7 n b y j n||a?6? d i j o b / n b y j n . j d / d p n - ? e? n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 130mhz, a in = -0.5dbfs, data output termina- tion = 50 , t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) (note 1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ovdd, avdd to gnd............................................-0.3v to +3.6v cma, cmb, refio, ina+, ina-, inb+, inb- to gnd ......................................................-0.3v to +2.1v clk+, clk-, sync, spen , cs , sclk, sdin to gnd ..........-0.3v to the lower of (v avdd + 0.3v) and +3.6v dclka, dclkb, d7aCd0a, d7bCd0b, dora, dorb to gnd..........-0.3v to the lower of (v ovdd + 0.3v) and +3.6v continuous power dissipation (t a = +70c) 48-pin thin qfn, 7mm x 7mm x 0.8mm (derate 40mw/c above +70c).............................................................3200mw operating temperature range ...........................-40c to +85c junction temperature ......................................................+150c storage temperature range .............................-65c to +150c lead temperature (soldering, 10s) .................................+300c soldering temperature (reflow) .......................................+260c parameter symbol conditions min typ max units dc accuracy resolution 8 bits integral nonlinearity inl f in = 3mhz -0.3 0.1 +0.3 lsb differential nonlinearity dnl f in = 3mhz -0.3 0.1 +0.3 lsb offset error oe internal reference -0.4 0.1 +0.4 %fs gain error ge external reference = 1.25v -1.5 0.3 +1.5 %fs analog inputs (ina+, ina-, inb+, inb-) (figure 3) differential input-voltage range v diff differential or single-ended inputs 1.5 v p-p common-mode input-voltage range v cm (note 2) 0.4 1.4 v fixed resistance, common mode, and differential mode > 100 input resistance r in differential input resistance, common mode connected to inputs 4 k input current i in switched capacitance common-mode input current, each input 74 a c par fixed capacitance to ground, each input 0.7 input capacitance c sample switched capacitance, each input 1.2 pf conversion rate maximum clock frequency f clk 130 mhz minimum clock frequency f clk 65 mhz data latency figures 9, 10 9 cycles n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units dynamic performance small-signal noise floor ssnf f in = 70mhz, < -35dbfs -49.8 dbfs f in = 3mhz 49.8 f in = 70mhz 49.0 49.8 signal-to-noise ratio snr f in = 175mhz 49.8 dbfs f in = 3mhz 49.3 f in = 70mhz 48.5 49.3 signal-to-noise plus distortion ratio sinad f in = 175mhz 49.3 db f in = 3mhz 77.0 f in = 70mhz 65.0 77.0 spurious-free dynamic range (2nd and 3rd harmonic) sfdr1 f in = 175mhz 77.0 dbc f in = 3mhz 69.0 f in = 70mhz 64.0 69.0 spurious-free dynamic range (4th and higher harmonics) sfdr2 f in = 175mhz 69.0 dbc f in = 3mhz -78.0 f in = 70mhz -78.0 -65.0 second harmonic hd2 f in = 175mhz -78.0 dbc f in = 3mhz -82.0 f in = 70mhz -82.0 -65.0 third harmonic hd3 f in = 175mhz -80.0 dbc f in = 3mhz -72.0 f in = 70mhz -72.0 -63.0 total harmonic distortion thd f in = 175mhz -72.0 dbc f in = 70mhz 1.5mhz, -7dbfs -80 third-order intermodulation im3 f in = 175mhz 2.5mhz, -7dbfs -75 dbc full-power bandwidth fpbw r source = 50 differential, -3db rolloff 850 mhz aperture delay t ad 850 ps aperture jitter t aj 0.3 ps rms overdrive recovery time 10% beyond full scale 1 cycles electrical characteristics (continued) (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 130mhz, a in = -0.5dbfs, data output termina- tion = 50 , t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) (note 1) n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d 4 _______________________________________________________________________________________ electrical characteristics (continued) (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 130mhz, a in = -0.5dbfs, data output termina- tion = 50 , t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) (note 1) parameter symbol conditions min typ max units interchannel characteristics f ina or f inb = 70mhz at -1dbfs 95 crosstalk f ina or f inb = 175mhz at -1dbfs 85 dbc gain match f in = 70mhz 0.05 db offset match f in = 70mhz 0.2 %fsr phase match f in = 70mhz 0.5 d eg r ees analog outputs (cma, cmb) cma, cmb output voltage v com default programmable setting 0.85 0.9 0.95 v internal reference refio output voltage v refout 1.23 1.25 1.27 v refio temperature coefficient tc ref < 60 ppm/c external reference refio input-voltage range v refin 1.25 +5/ -10% v refio input resistance r refin 10 20% k clock inputs (clk+, clk-)differential mode differential clock input voltage 0.4 to 2.0 v p-p self-biased 1.2 differential input common-mode voltage dc-coupled clock signal 1.0 to 1.4 v differential, default 10 k differential, programmable internal termination selected 100 input resistance r clk common mode 9 k input capacitance c clk to ground, each input 3 pf clock inputs (clk+, clk-)single-ended mode (v clk- < 0.1v) single-ended mode selection threshold (v clk- ) 0.1 v allowable logic swing (v clk+ ) 0 - v avdd v single-ended clock input high threshold (v clk+ ) 1.5 v single-ended clock input low threshold (v clk+ ) 0.3 v v clk+ = v avdd = 1.8v or 3.3v +0.5 input leakage (clk+) v clk+ = 0v -0.5 a input leakage (clk-) v clk- = 0v -150 -50 a input capacitance (clk+) 3pf n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d _______________________________________________________________________________________ 5 electrical characteristics (continued) (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 130mhz, a in = -0.5dbfs, data output termina- tion = 50 , t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) (note 1) parameter symbol conditions min typ max units clock input (sync) allowable logic swing 0 - v avdd v sync clock input high threshold 1.5 v sync clock input low threshold 0.3 v v sync = v avdd = 1.8v or 3.3v +0.5 input leakage v sync = 0v -0.5 a input capacitance 4.5 pf digital inputs (shdn, spen ) allowable logic swing 0 - v avdd v input high threshold 1.5 v input low threshold 0.3 v v shdn /v spen = v avdd = 1.8v or 3.3v +0.5 input leakage v shdn /v spen = 0v -0.5 a input capacitance c din 3pf serial-port inputs (sclk, sdin, cs , where spen = 0v)serial-port control mode allowable logic swing 0 - v avdd v input high threshold 1.5 v input low threshold 0.3 v v sclk /v sdin /v cs = v avdd = 1.8v or 3.3v +0.5 input leakage v sclk /v sdin /v cs = 0v -0.5 a input capacitance c din 3pf serial-port inputs (sclk, sdin, cs , where spen = v avdd )parallel control mode (figure 5) v sclk /v sdin /v cs = v avdd = 1.8v 7 12 17 input pullup current v sclk /v sdin /v cs = v avdd = 3.3v 16 21 26 a v sclk /v sdin /v cs = 0v, v avdd = 1.8v -65 -50 -35 input pulldown current v sclk /v sdin /v cs = 0v, v avdd = 3.3v -105 -90 -75 a v avdd = 1.8v 1.35 1.45 1.55 open-circuit voltage v oc v avdd = 3.3v 2.58 2.68 2.78 v digital outputs (cmos mode 75 , d0Cd7 (a and b channel), dclka, dclkb, dora, dorb) output-voltage low v ol i sink = 200a 0.2 v output-voltage high v oh i source = 200a v ovdd - 0.2 v v ovdd applied +0.5 three-state leakage current i leak gnd applied -0.5 a n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d 6 _______________________________________________________________________________________ electrical characteristics (continued) (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 130mhz, a in = -0.5dbfs, data output termina- tion = 50 , t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) (note 1) parameter symbol conditions min typ max units power-management characteristics wake-up time from shutdown t wake internal reference, c refio = 0.1f (10 )5ms wake-up time from standby t wake internal reference 15 s serial-port interface timing (note 2) (figure 7) sclk period t sclk 50 ns sclk to cs setup time t css 10 ns sclk to cs hold time t csh 10 ns sdin to sclk setup time t sds serial-data write 10 ns sdin to sclk hold time t sdh serial-data write 0 ns sclk to sdin output data delay t sdd serial-data read 10 ns timing characteristicsdual bus parallel mode (figure 9), (default timing see table 5) clock pulse-width high t ch 3.85 ns clock pulse-width low t cl 3.85 ns clock duty cycle t ch /t clk 30 to 70 % c l = 10pf, v ovdd = 1.8v (note 2) 10.3 12.6 14.9 data delay after rising edge of clk+ t dd c l = 10pf, v ovdd = 3.3v 11.4 ns data to dclk setup time t setup c l = 10pf, v ovdd = 1.8v (note 2) 6.0 6.7 ns data to dclk hold time t hold c l = 10pf, v ovdd = 1.8v (note 2) 0.4 1.0 ns timing characteristicsmultiplexed bus parallel mode (figure 10), (default timing see table 5) clock pulse-width high t ch 3.85 ns clock pulse-width low t cl 3.85 ns clock duty cycle t ch /t clk 30 to 70 % c l = 10pf, v ovdd = 1.8v (note 2) 6.9 9.2 11.5 data delay after rising edge of clk+ t dd c l = 10pf, v ovdd = 3.3v 8.5 ns data to dclk setup time t setup c l = 10pf, v ovdd = 1.8v (note 2) 1.3 2.3 ns data to dclk hold time t hold c l = 10pf, v ovdd = 1.8v (note 2) 0.7 1.5 ns dclk duty cycle t dch /t clk c l = 10pf, v ovdd = 1.8v (note 2) 38 50 64 % mux data duty cycle t cha /t clk c l = 10pf, v ovdd = 1.8v (note 2) 38 50 62 % timing characteristicssynchronization (figure 12) setup time for valid clock edge t suv edge mode (note 2) 0.7 ns hold-off time for invalid clock edge t ho edge mode (note 2) 0.5 ns minimum synchronization pulse width relative to input clock period 2 cycles n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d _______________________________________________________________________________________ 7 electrical characteristics (continued) (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 130mhz, a in = -0.5dbfs, data output termina- tion = 50 , t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) (note 1) parameter symbol conditions min typ max units power requirements low-level v avdd 1.7 1.9 analog supply voltage v avdd high-level v avdd (regulator mode, invoked automatically) 2.3 3.5 v digital output supply voltage v ovdd 1.7 3.5 v dual channel 82 95 single channel active 48 standby mode 11.5 15 power-down mode 0.65 0.9 analog supply current i avdd power-down mode, v avdd = 3.3v 1.6 ma dual channel 148 171 dual channel, v avdd = 3.3v 271 single channel active 86 standby mode 21 27 power-down mode 1.2 1.6 analog power dissipation p da power-down mode, v avdd = 3.3v 2.9 mw dual-channel mode, c l = 10pf 22 digital output supply current i ovdd power-down mode < 0.1 ma note 1: specifications t a +25c guaranteed by production test, specifications t a < +25c guaranteed by design and characterization. note 2: guaranteed by design and characterization. 175mhz two-tone imd plot max19507 toc06 frequency (mhz) amplitude (dbfs) 0 204060 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 f in1 = 172.50053mhz f in2 = 177.48741mhz 70mhz two-tone fft plot max19507 toc05 frequency (mhz) amplitude (dbfs) 0 204060 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 f in1 = 71.49905mhz f in2 = 68.502129mhz 175mhz input fft plot max19507 toc04 frequency (mhz) amplitude (dbfs) 0 204060 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 f in = 175.105057mhz a in = -0.508dbfs snr = 49.225db sinad = 49.204db thd = -72.411dbc sfdr1 = 80.172dbc sfdr2 = 69.998dbc 70mhz input fft plot max19507 toc03 frequency (mhz) amplitude (dbfs) 0 204060 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 f in = 70.1088714mhz a in = -0.531dbfs snr = 49.187db sinad = 49.172db thd = -73.779dbc sfdr1 = 76.498dbc sfdr2 = 71.834dbc 3mhz single-ended input fft plot max19507 toc02 frequency (mhz) amplitude (dbfs) 0 204060 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 f in = 3.05381775mhz a in = -0.496dbfs snr = 49.281db sinad = 49.232db thd = -68.700dbc sfdr1 = 69.821dbc sfdr2 = 68.781dbc n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d 8 _______________________________________________________________________________________ ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ?o ?+v (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 130mhz, a in = -0.5dbfs, data output termina- tion = 50 , t a = +25c, unless otherwise noted.) 3mhz input fft plot frequency (mhz) amplitude (dbfs) max19507 toc01 0 204060 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 f in = 2.99827576mhz a in = -0.543dbfs snr = 49.135db sinad = 49.120db thd = -73.810dbc sfdr1 = 79.951dbc sfdr2 = 68.821dbc integral nonlinearity vs. digital output code digital output code inl (lsb) max19507 toc07 0 64 128 192 256 -0.10 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.10 max19507 toc08 differential nonlinearity vs. digital output code digital output code dnl (lsb) 0 64 128 192 256 -0.10 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.10 performance vs. input frequency max19507 toc09 input frequency (mhz) performance (dbfs) 300 400 200 100 55 60 65 70 75 80 85 45 50 0 sfdr1 sfdr2 -thd sinad snr analog supply current vs. supply voltage max19507 toc18 supply voltage (v) analog supply current (ma) 1.90 1.85 1.80 1.75 1.70 78 80 82 84 86 88 90 76 1.65 1.95 performance vs. analog input amplitude max19507 toc11 analog input amplitude (dbfs) performance (dbfs) -10 -20 -30 -40 -50 -60 0 sfdr2 sfdr1 -thd sinad snr 55 60 65 70 75 80 85 45 50 single-ended performance vs. input frequency max19507 toc10 input frequency (mhz) 60 20 40 0 sfdr2 sfdr1 -thd sinad snr single-ended performance (dbfs) 55 60 65 70 75 80 85 45 50 ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ?o ?+v )? * (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 130mhz, a in = -0.5dbfs, data output termina- tion = 50 , t a = +25c, unless otherwise noted.) n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d _______________________________________________________________________________________ 9 performance vs. sampling frequency max19507 toc12 sampling frequency (msps) performance (dbfs) 130 120 100 110 90 140 sfdr2 sfdr1 -thd sinad snr 55 60 65 70 75 80 85 45 50 performance vs. common-mode voltage max19507 toc13 common-mode voltage (v) performance (dbfs) 1.35 1.15 0.95 0.75 0.55 0.35 sfdr2 sfdr1 -thd sinad snr 55 60 65 70 75 80 85 45 50 performance vs. analog supply voltage max19517 toc14 analog supply voltage (v) performance (dbfs) 1.85 1.75 1.65 1.95 sfdr2 sfdr1 -thd sinad snr 55 60 65 70 75 80 85 45 50 performance vs. analog supply voltage max19507 toc15 analog supply voltage (v) performance (dbfs) 3.3 2.8 2.3 sfdr2 sfdr1 -thd sinad snr 55 60 65 70 75 80 85 45 50 analog supply current vs. sampling frequency max19507 toc16 sampling frequency (mhz) analog supply current (ma) 130 120 110 100 135 125 115 105 65 70 75 80 85 90 60 90 95 140 analog supply current vs. temperature max19507 toc17 temperature ( c) analog supply current (ma) 80 60 40 20 0 -20 75 80 85 90 95 70 -40 10 ______________________________________________________________________________________ ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ?o ?+v )? * (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 130mhz, a in = -0.5dbfs, data output termina- tion = 50 , t a = +25c, unless otherwise noted.) analog supply current vs. supply voltage max19507 toc19 supply voltage (v) analog supply current (ma) 3.5 3.3 3.1 2.9 2.7 2.5 78 80 82 84 86 88 90 76 2.3 n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d digital supply current vs. sampling frequency max19507 toc20 sampling frequency (msps) digital supply current (ma) 120 110 100 5 10 15 20 25 0 90 130 v ovdd = 1.8v digital supply current vs. sampling frequency max19507 toc21 sampling frequency (msps) digital supply current (ma) 120 110 100 5 10 15 20 25 30 35 40 45 50 0 90 130 v ovdd = 3.6v digital supply current vs. temperature maax19507 toc22 temperature ( c) digital supply current (ma) 60 10 25 30 35 40 45 50 20 -40 v ovdd = 3.6v v ovdd = 1.8v digital supply current vs. supply voltage supply voltage (v) digital supply current (ma) max19507 toc23 1.8 2.3 2.8 3.3 0 5 10 15 20 25 30 35 40 45 dual bus digital supply current vs. supply voltage supply voltage (v) digital supply current (ma) max19507 toc24 1.7 2.2 2.7 3.2 0 5 10 15 20 25 30 35 40 45 50 multiplexed bus performance vs. clock duty cycle max19507 toc25 clock duty cycle (%) performance (dbfs) 60 40 50 60 65 70 75 80 85 45 50 55 30 sfdr2 sfdr1 -thd sinad snr performance vs. temperature max19507 toc26 temperature ( c) performance (dbfs) 60 10 -40 sfdr2 sfdr1 -thd sinad snr 60 65 70 75 80 85 45 50 55 gain error vs. temperature max19517 toc27 temperature ( c) gain error (%) 60 10 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05 -0.05 -40 ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ?o ?+v )? * (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 130mhz, a in = -0.5dbfs, data output termina- tion = 50 , t a = +25c, unless otherwise noted.) common-mode voltage vs. temperature max19507 toc30 temperature ( c) common-mode voltage (v) 60 10 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 -40 v cm = 1.35v v cm = 1.2v v cm = 1.05v v cm = 0.9v v cm = 0.75v v cm = 0.6v v cm = 0.45v offset error vs. temperature max19507 toc28 temperature ( c) offset error (mv) 60 10 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 -0.7 -40 n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d ______________________________________________________________________________________ 11 reference voltage vs. temperature max19507 toc29 temperature ( c) reference voltage (v) 60 10 1.2453 1.2474 1.2495 1.2516 1.2432 -40 gain error vs. supply voltage supply voltage (v) gain error (%) max19507 toc31 1.6 2.1 2.6 3.1 3.6 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 regulator mode input current vs. common-mode voltage common-mode voltage (v) input current ( a) max19507 toc32 0.4 0.6 0.8 1.0 1.2 1.4 40 50 60 70 80 90 100 110 n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d 12 ______________________________________________________________________________________ ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` [ m? 1, 12, 13, 48 avdd 2 cma 3 ina+ 4 ina- 5 spen 6 refio 7 shdn 8 i.c. 9 inb+ 10 inb- 11 cmb 14 sync 15 clk+ 16 clk- 17, 18 gnd 19 dorb 20 dclkb 21, 22 i.c. 23 d0b 24 d1b 25, 36 ovdd 26 d2b 27 d3b 28 d4b 29 d5b 30 d6b 31 d7b 32, 33 i.c. 34 d0a 35 d1a 37 d2a 38 d3a 39 d4a [ m a ? y ???1 ? 1 / 2 g?? s ? b w e er? ) 2 5 9 * [ ) 2 3 2 4 *l 5? h o e 0x b| a yr??1 ?e 0x b| y r?u 0x b| y r? ? ??3?i t q j'q?? ?3 '@ > y+ ?er? 0r'] ?e 0 - m? 1 / 2 g|?? sl 5? h o e ?j] ?es |g??l ?er? 0r ) s f g j p * ] j ?3?i ? <?? + spen ? ?3 )@ > y+ * ? t i e o| ]?? @ ?? ]/ {y { 0x c| y r?u 0x c| y r? ? 0x c| a yr??1 ?e ? j? y+4[r? ?r?u ?r? ?? + d m l . {? d m l , ?] ] ?3 ?r? e d m l , 0 d m l .???? j ?r? ? s???r? [ f q ! ) a fd * {?? 0x ck ?" 0x ck ? ? ]/ {y { 0x c|?k r? 1? ) m t c * 0x c|?k r? 2? k ???10 - 1 / 2 g?? s ? p w e er?l 5? h o e 0x c|?k r? 3? 0x c|?k r? 4? 0x c|?k r? 5? 0x c|?k r? 6? 0x c|?k r? 7? 0x c|?k r? 8? ) n t c * ]/ {y { 0x b|?k r? 1? ) m t c * 0x b|?k r? 2? 0x b|?k r? 3? 0x b|?k r? 4? 0x b|?k r? 5? n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d ______________________________________________________________________________________ 13 ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` .? n b y 2 : 6 1 8g ? 2 1 ]? j z# ? )d 2 * ? ?# t |4 s ? r ]?"?r?g?m ? ?2e? 0 - z#r?ur| ? : ?2e z#t | ? sr??1t ?k r i" ? j ? r??1 [k r i? .|?? 9m@?? k ? ?u?w? ? b e d w|??@i?y i d 3?,? n b y 2 : 6 1 8| ? vd y r? [ a y ?e y r?g s+u y r? ) j o b , 0 j o b . t j o c , 0 j o c . * ? {?r?g )d 4 *ir?g ] r?g s0 -r? t0? +us?? r? l ~ .r?g s ?rg z# b e d g?1 ?r @? : ?2e ? k r ? +?r? ] *(g?g??? ??ur? a y?1 a y?? -?j] tw0 - 3 l ? ?] ? ? ]b|g s? j]?1 [? c ? ] b|r?? ? a yr??1 ??r?? -0 -$1( x ||f?? tw0 - >??$b|] @?] 3 l ? r?? ? )d 4 *?]? r?? ? ?|1 ] s ]?r? a y?1 a yr? ?e?10 - - @??? 1 / 5 6 w? 2 / 4 6 w *?2 1 / 2 6 w?[? ?r ?? ????? 1 / : 1 wb ? ??? ? ]q?? 5 a yr ?e ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` [ m? )? * 40 d5a 41 d6a 42 d7a 43 dora 44 dclka 45 sdin/format 46 sclk/div 47 cs /outsel ep max19507 + ? digital error correction flash adc x2 dac stage 2 in_+ in_- stage 1 stage 9 stage 10 end of pipeline d0_ through d7_ d 2 / ! z# ? j vd [ m a ? 0x b|?k r? 7? 0x b|?k r? 8? ) n t c * 0x bk ?" 0x bk ? ? t q jk ?r? 0 ?+i spen ???3 ?rk ?r?i spen ? ?3 ??rk ? ?+ r ? 0 ? j?i spen ???3 ?r ?i spen ? ?3 + ? j?r? >? 0k ?r y+i spen ???3 ? >? i spen ? ?3 ? k ?r y+ a fd] {? h o e {um a ??2 " 2z 0x b|?k r? 6? n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d 14 ______________________________________________________________________________________ t/h ina+ cma refio cmb ina- output drivers data and output format pipeline adc pipeline adc clock clock digital error correction internal reference generator reference and bias system digital error correction duty- cycle equalizer clock divider d0aCd7a dclkb shdn gnd dorb d0bCd7b ovdd (1.8v to 3.3v) avdd (1.8v or 2.5v to 3.3v) dclka dora t/h inb+ inb- clk+ clk- sync cs sclk sdin serial port and control registers internal control 1.8v internal regulator and power control spen max19507 max19507 c par 0.7pf ina+ *v com *v com programmable from 0.45v to 1.35v. see common-mode register (08h) avdd cma 2k 2k c sample 1.2pf c sample 1.2pf c par 0.7pf ina- avdd sampling clock r switch 120 r switch 120 d 3 / ! ? vd d 4 / ! ]g? ) u 0 i *? 5 n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d ______________________________________________________________________________________ 15 ?er? 0r ) s f g j p * s f g j p ? ?e?1- s b e d| x ? *?d 5 ? < ?| ?e? d]r?1 ?e? ] ? e?1r?1 3 - |@0 - 2 1 l ? +u s f g j p ? 1 / 2 g?? s s f g j pl 5? h o er ?1r?u ? ? [?3t ? 5? ?? 5? i? b e d x ? *?|] ?e?1+? s f g j p |j]?1 -2 ? b e d x ? *???s *? ? , 6 0 . 2 6 & s f g j p? b e d|dr =k?? w g t > ! 2 / 6 ! y ! \ w s f g j p 0 2 / 3 6 ^ ! p [ { > -0 - y? 1 <? n b y 2 : 6 1 8| ?+ y+ ? t q j { > -2 <??? ??2 ?@ > - <??"| ? ? y+0 - spen r?? s spen q ????3 ? t q j { > s spen q?? ?3 ? @ > @ > @ > ? [ m { > ????"| ? ? s spen {? b w e e'@ > ?[ m ?? l - 2 < ?|@ >r?? d?l d 6 bandgap reference buffer 1.250v refio internal gainbypass refio external gain controldrive refio scale and level shift internal reference (controls adc gain) 10k 0.1 f external bypass d 5 / ! < ?| ?e? d 36k 156k cs sclk sdin avdd 29/32 avdd decoder to control logic 23/32 avdd 3/32 avdd d 6 / ! < ?|@ >r?? d spen sdin/format sclk/div cs /outsel description 0 sdin sclk cs spi interface active. features are programmed through the serial port (see the serial programming interface section). 1 0 x x twos complement 1 avdd x x offset binary 1 unconnected x x gray code 1 x 0 x clock divide-by-1 1 x avdd x clock divide-by-2 1 x unconnected x clock divide-by-4 1 x x 0 cmos (dual bus) 1 x x avdd mux cmos (channel a data bus) 1 x x unconnected mux cmos (channel b data bus) - 2 / ! @ >[ m ? y ! > ! ? n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d 16 ______________________________________________________________________________________ r { > >0 - cs t e j o [ t d m lr? n b y 2 : 6 1 8| <? @ ?r i cs ???3 ? t d m l|? ?r k ????$? t e j oi cs ? ?3 n b y 2 : 6 1 8 ? r t e j o [ t d m l|k ? ? ?( 0vw+ ? d t? ?$u ?3 t e j o -+?s <? @|rk ?r >}? 0g2e|w ?r? ?? <? ?t j?? [ 0v? v? n b y 2 : 6 1 8? ??k ? ?v? n b y 2 : 6 1 8 t - n b y 2 : 6 1 8 d 7?,? >0g2e? t e j o?i? ?0g2e ?rvw+ tw+ ) 1t-vw+ 2t-w+ *2 ? 8??? sv? ts| @??" ? 9 t e j o? ? @k ????? [k ???v? [s ?? n t c?w+e . n b y 2 : 6 1 8 >? t d m l? 9 ? ?? ?| ]? ssk ? ) e 8 *?? t e j o?? t e j or?|"c? .? ?2 <??? t d m l| ? 9 ? ? ? -2 +? t e j oq?2 ?|k ??? t d m l| ]??? t e j ow+|rk ?? t d m l| ? ????d 8 ?.| > ?d r/w a6 a4 a5 a2 a3 a0 a1 d7 d6 d4 d5 d2 d3 d0 d1 r/w 0 = write 1 = read cs sclk sdin address data write or read cs t css t csh t sdd t sds t sdh t sclk sclk sdin write read d 7 / ! >0g2e d 8 / ! > ?d n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d ______________________________________________________________________________________ 17 bit no. value description 7 0 reserved 6 0 reserved 5 0 or 1 1 = rom read in progress 4 0 or 1 1 = rom read completed and register data is valid (checksum is ok) 3 0 reserved 2 1 reserved 1 0 or 1 reserved 0 0 or 1 1 = duty-cycle equalizer dll is locked - 3 / ! @ 1 b i|? ? address por default function 00h 00000011 power management 01h 00000000 output format 02h 00000000 digital output power management 03h 01101101 data/dclk timing 04h 00000000 c h a d ata outp ut ter m i nati on contr ol 05h 00000000 c h b d ata outp ut ter m i nati on contr ol 06h 00000000 c l ock d i vi d e/d ata for m at/test p atter n 07h reserved reserveddo not use 08h 00000000 common mode 0ah software reset - 4 / ! ? @ ??? 1 b i| @?p ? @ sk ? 6 b iv? @ 1 b i ? @ ???r ?w+ ?? < ? @? ??u ??? @ 1 b i|w+ ) ? ? ? ? :c?l - 3?,|g?? t i e or? )[ m 8 *? <??@ y ?? ?? .| t ?? @?c ? ? ?? ? ?? ? t i e o > 2 ? n b y 2 : 6 1 8 t i e o > 1 ) ? ur] ?+? ? @ ?? ) 1 1 i * bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hps_shdn1 stby_shdn1 c h b_on _s h d n 1c h a_o n _s h d n 1 hps_shdn0 stby_shdn0 chb_on_shdn0 c h a_o n _s h d n 0 n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d 18 ______________________________________________________________________________________ hps_shdn0 stby_shdn0 cha_on_shdn0 chb_on_shdn0 shdn input = 0* hps_shdn1 stby_shdn1 cha_on_shdn1 chb_on_shdn1 shdn input = 1** x 0 0 0 complete power-down 0 0 0 1 channel b active, channel a full power-down 0 0 1 0 channel a active, channel b full power-down 0 x 1 1 channels a and b active 0 1 0 0 channels a and b in standby mode 0 1 0 1 channel b active, channel a standby 0 1 1 0 channel a active, channel b standby 1 1 0 0 channels a and b in standby mode 1 x 1 x channels a and b active, output is averaged 1 x x 1 channels a and b active, output is averaged <??? r ?+ ) 1 2 i * ??? i q t ` t i e o 2 [ i q t ` t i e o 1 -2? b , c y+ ? y+ y 0x| ? +s3 ? n v y ` d i?? r ) b , c * 0 3k ?|# bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 bit_order_b bit_order_a mux_ch mux 0 * i t i e o ! > ! 1 i q t ` t i e o 1 t u c z ` t i e o 1 d i b ` p o ` t i e o 1 [ d i c ` p o ` t i e o 1?i ** i t i e o ! > ! 2 i q t ` t i e o 2 t u c z ` t i e o 2 d i b ` p o ` t i e o 2 [ d i c ` p o ` t i e o 2?i y ! > ! ? ?? i i q t ` t i e o ` ! > ! 2 ! ) b , c y+ * d i b ` p o ` t i e o ` [ d i c ` p o ` t i e o `? ?? 1c - ?? ? tw ?? ? 8 7 6? ? 1u? ?+ ? 5? c j u ` p s e f s ` c? s d i cr?? (6 1 ! > ! ?m?c|k ?#[ m? ) ?? * 2 ! > ! sk ?#[ m|? (6 ? 4? c j u ` p s e f s ` b? s d i br?? (6 1 ! > ! ?m?c|k ?#[ m? ) ?? * 2 ! > ! sk ?#[ m|? (6 ? 3? n v y ` d i? ?k ?#? 1 ! > ! ? d i b? ?k ?r )e r d i bk ?2 ?r d i ck ? * ! ) ?? * 2 ! > ! ? d i c? ?k ?r )e r d i ck ?2 ?r d i bk ? * ? 2? n v y?k r y+ 1 ! > ! w 5k ?#r y+ ) ?? * 2 ! > ! ] 5 ?k ?#r y+ n v y ` d i? r# ? 1? ? 1u? ?+ n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d ______________________________________________________________________________________ 19 k r?? ) 1 3 i * bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x x x x pd_dout_1 pd_dout_0 dis_dor dis_dclk ? 8 C 5? ? 2 ? 4 3? q e ` e p v u ` 2 q e ` e p v u ` 1? ?k r? <? 1 1 ! > ! k r?? ) ?? * 1 2 ! > ! k r???3 2 1 ! > ! k r?? 2 2 ! > ! k r? ?3 ? 2? e j t ` e p s? e p sq? 1 ! > ! e p s?i ) ?? * 2 ! > ! e p s )? * ? 1? e j t ` e d m l? e d m lq? 1 ! > ! e d m l?i ) ?? * 2 ! > ! e d m l )? * n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d 20 ______________________________________________________________________________________ k ? 0 e d m l ? ) 1 4 i * bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 da_bypass dly_half_t dclktime_2 dclktime_1 dclktime_0 dtime_2 dtime_1 dtime_0 ? 8? e b ` c z q b t t?k ?el 5 1 ! > ! *e ?+ y+ ) ?? * 2 ! > ! l 5k ?e?#$?r? ?|rk ??"c ?? e u j n f ! > ! 1 1 1 c - ?? ?uk ?t | .m?? 7 o t ? 7? e m z ` i b m g ` u?k ? [ e d m l? u 0 3 1 ! > ! *e ?+ y+?? 2 ! > ! k ? [ e d m lr? u 0 3 ! ) ?? * ? n v yk ?# y+ ? 6 5 4? e d m l u j n f ` 3 e d m l u j n f ` 2 e d m l u j n f ` 1? e d m l ?s ) <? y 0x * 1 1 1 ! > ! *e ?+ y+ 1 1 2 ! > ! , u 0 2 7 1 2 1 ! > ! , 3 u 0 2 7 1 2 2 ! > ! , 4 u 0 2 7 2 1 1 ! > ! ? ??' 2 1 2 ! > ! . 2 u 0 2 7 ! ) ?? * 2 2 1 ! > ! . 3 u 0 2 7 ! 2 2 2 ! > ! . 4 u 0 2 7 ! ? 3 2 1? e u j n f ` 3 e u j n f ` 2 e u j n f ` 1?k ? ?s ) <? y 0x * 1 1 1 ! > ! *e ?+ y+ 1 1 2 ! > ! , u 0 2 7 1 2 1 ! > ! , 3 u 0 2 7 1 2 2 ! > ! , 4 u 0 2 7 2 1 1 ! > ! ? ??' 2 1 2 ! > ! . 2 u 0 2 7 ! ) ?? * 2 2 1 ! > ! . 3 u 0 2 7 ! 2 2 2 ! > ! . 4 u 0 2 7 n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d ______________________________________________________________________________________ 21 d i bk ?r { <? ) 1 5 i * bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x x ct_dclk_2_a ct_dclk_1_a ct_dclk_0_a ct_data_2_a ct_data_1_a ct_data_0_a ? 8 7? ? 2 ? 6 5 4? d u ` e d m l ` 3 ` b d u ` e d m l ` 2 ` b d u ` e d m l ` 1 ` b? d i b ! e d m l { <? 1 1 1 ! > ! 6 1 ) ?? * 1 1 2 ! > ! 8 6 1 2 1 ! > ! 2 1 1 1 2 2 ! > ! 2 6 1 2 y y ! > ! 4 1 1 ? 3 2 1? d u ` e b u b ` 3 ` b d u ` e b u b ` 2 ` b d u ` e b u b ` 1 ` b? d i bk ?r { <? 1 1 1 ! > ! 6 1 ) ?? * 1 1 2 ! > ! 8 6 1 2 1 ! > ! 2 1 1 1 2 2 ! > ! 2 6 1 2 y y ! > ! 4 1 1 d i ck ?r { <? ) 1 6 i * bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x x ct_dclk_2_b ct_dclk_1_b ct_dclk_0_b ct_data_2_b ct_data_1_b ct_data_0_b ? 8 7? ? 2 ? 6 5 4? d u ` e d m l ` 3 ` c d u ` e d m l ` 2 ` c d u ` e d m l ` 1 ` c? d i c ! e d m l { <? 1 1 1 ! > ! 6 1 ) ?? * 1 1 2 ! > ! 8 6 1 2 1 ! > ! 2 1 1 1 2 2 ! > ! 2 6 1 2 y y ! > ! 4 1 1 ? 3 2 1? d u ` e b u b ` 3 ` c d u ` e b u b ` 2 ` c d u ` e b u b ` 1 ` c? d i ck ?r { <? 1 1 1 ! > ! 6 1 ) ?? * 1 1 2 ! > ! 8 6 1 2 1 ! > ! 2 1 1 1 2 2 ! > ! 2 6 1 2 y y ! > ! 4 1 1 n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d 22 ______________________________________________________________________________________ ? j? 0k ? ?+ 0?b y? ) 1 7 i * ? ) 1 8 i * ??v? ? @ bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 test_pattern test_data format_1 format_0 term_100 sync_mode div1 div0 ? 8? u f t u ` q b u u f s o??b y?? 1 ! > ! - 1? u 3 6 6 ! )?$ ?? *@? ? ? - )g ?? ?+ * ! ) ?? * 2 ! > ! ? y k ?0x? cr? e \ 8 ; 1 ^ ! > ! 1 2 1 2 1 2 1 2 e p s ! > ! 2 [ e \ 8 ; 1 ^ ! > ! 2 1 2 1 2 1 2 1 e p s ! > ! 1 ? 7? u f t u ` e b u b?k ??b y+ 1 ! > ! *ek ?r ) ?? * 2 ! > ! r?bk ? y? ? 6 5? g p s n b u ` 2 g p s n b u ` 1?k ?? ?+ 1 1 ! > ! ??w i ) ?? * 1 2 ! > ! ?$ ?? 2 1 ! > ! ? ? i 2 2 ! > ! ??w i ? 4? u f s n ` 2 1 1?? 2 1 1 ?r? { 1 ! > ! ? { ) ?? * 2 ! > ! ? j ?r? k { 2 1 1 { ? 3? t z o d ` n p e f? j?4[ y+? 1 ! > ! ?? y+ )d 2 2 * ! ) ?? * 2 ! > ! ? y+ )d 2 3 * ? 2 1? e j w 2 e j w 1?r? ? j?? 1 1 ! > ! ?? j? ) ?? * 1 2 ! > ! 3 j? 2 1 ! > ! 5 j? 2 2 ! > ! ?? j? n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d ______________________________________________________________________________________ 23 a y ) 1 9 i * ? h ?? ) 1 b i * bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cmi_self_b cmi_adj_2_b cmi_adj_1_b cmi_adj_0_b cmi_self_a cmi_adj_2_a cmi_adj_1_a cmi_adj_0_a ? 8? d n j ` t f m g ` c? d i cr? a y { y r? 1 ! > ! ] a y?1y+ur? ) ?? * 2 ! > ! 0 - 3 l ? s] a y?1+u y r? ? 7 6 5? d n j ` b e k ` 3 ` c d n j ` b e k ` 2 ` c d n j ` b e k ` 1 ` c? d i cr? a y?1s 1 1 1 ! > ! 1 / : 1 1 w ! ) ?? * 1 1 2 ! > ! 2 / 1 6 1 w 1 2 1 ! > ! 2 / 3 1 1 w 1 2 2 ! > ! 2 / 4 6 1 w 2 1 1 ! > ! 1 / : 1 1 w 2 1 2 ! > ! 1 / 8 6 1 w 2 2 1 ! > ! 1 / 7 1 1 w 2 2 2 ! > ! 1 / 5 6 1 w ? 4? d n j ` t f m g ` b? d i br? a y { y r? 1 ! > ! ] a y?1y+ur? ) ?? * 2 ! > ! 0 - 3 l ? s] a y?1+u y r? ? 3 2 1? d n j ` b e k ` 3 ` b d n j ` b e k ` 2 ` b d n j ` b e k ` 1 ` b? d i br? a ys 1 1 1 ! > ! 1 / : 1 1 w ! ) ?? * 1 1 2 ! > ! 2 / 1 6 1 w 1 2 1 ! > ! 2 / 3 1 1 w 1 2 2 ! > ! 2 / 4 6 1 w 2 1 1 ! > ! 1 / : 1 1 w 2 1 2 ! > ! 1 / 8 6 1 w 2 2 1 ! > ! 1 / 7 1 1 w 2 2 2 ! > ! 1 / 5 6 1 w ? 8 C 1? t x s f t f u?v? 6 b i ?? h ?? ?r? r? ? { >? ? j?|g ? v n b y 2 : 6 1 8 {j]? j ? t] ] ?3 ??# ? j ? ?+? s? j ? {? d m l , [ d m l .r? ? ? y+] p ar? a y?12?? c ? ] ? + a y?1?"?? ?| 2 w? 2 / 5 w ?r? a y * ? ? j ?g s -2g? ? ]?#] ?+? s d m l . {? h o e@& ] ?3g sq? d m l ,r?i d m l .r? {? ) tw? o??? ? y + 6? w| ?" * ? j?]t ] ?3 ($0 5 ? j? n b y 2 : 6 1 8 ? ? j??20 - >?? e j w 1 [ e j w 2' ? j? ? ? j??2|.g? ?l ? j? 0k ? ?+ 0?b y? @ ) 1 7 i * tw? @ > |? ) spen > 2 *|' e j wr?' ? j? n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d 24 ______________________________________________________________________________________ clk+ 100 termination (programmable) self-bias turned off for single-ended clock or power-down. clk- gnd avdd 10k 20k 5k 5k 50 50 2:1 mux select threshold d 9 / ! < ?| ?r?? d dclk data, dor sample clock n n+1 sample on rising edge n+2 n+4 n+5 n-9 n-8 n-10 n-7 n-6 n-5 n-4 t clk t setup t ch t dd t dc t hold t cl dual-bus output mode sample clock is the derived clock from (clk+ - clk-)/clock divider, in_ = in_+ - in_-. sampling instant sampling instant sampling instant sampling instant sampling instant sampling instant in_ t ad n+3 d : / ! w#r y+ ? n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d ______________________________________________________________________________________ 25 ; ?g d : [d 2 1? ? ?r? [r y r?g0 h [k ?r? .| n b y 2 : 6 1 8?g ?|? ? ?rg 3 - : ?|]? ?? e d m l |? ?r?ik ?? ? j?b|g ? ? j? ?|] ? ?+?? [(clk+ - clk-)/divider] 4[ g ? j? ] ?|$? -;| g q h b ? <? t n b y 2 : 6 1 8| ?y4$? y? 1+ - 24[] ?? ??4[ [ ?4[ ? j? 0k ? ?+ 0?b y? @ ) 1 7 i *| t z o d ` n p e f )? 3? *? 4[ y+@ s t z o dr?q?? ?3 ?r4[ ??4[ y+ t z o d ` n p e f > 1 ) ?? *? ? t z o d? ? ) #? x p a [? . *? ?|? 4 r? ? ) d m l * |? ?? j?r" -(??$ )d 2 2 * ?4[ y+ t z o d ` n p e f > 2? ? t z o d? ? ) #? x p a [? . *? ?|? 4 r? ? ) d m l *|? ? j?r???? 1 t z o d|?i? ? ? j? ?? ?? d m l|? 5 ) 0 3 y+ * t ? 6 ) 0 5 y+ *? ? )d 2 3 * dclk data, dor sample clock n-9 cha chb n-9 n-8 cha chb n-8 chb n-10 n-7 cha chb n-7 n-6 cha chb n-6 n-5 cha chb n-5 n-4 cha chb n-4 mux output mode in_ sampling instant sampling instant sampling instant sampling instant sampling instant sampling instant t ad n n+1 n+2 n+4 n+5 n+3 t ch t cl sample on rising edge t dc t dd t cha t dch t setup t hold t hold t dcl t setup t chb sample clock is the derived clock from (clk+ - clk-)/clock divider, in_ = in_+ - in_-. mux_ch (bit 2, output format 01h) determines the output bus and which channel data is presented. t clk d 2 1 / ! ?r y+ ? n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d 26 ______________________________________________________________________________________ sync sync 2x input clk 4x input clk 1x divided clk (state) 1x divided clk (state) t suv = set-up time for valid clock edge. t ho = hold-off time for invalid clock edge. divide-by-2 slip synchronization 1234 1234 slip slip (1) (0) (1) (0) (1) (0) (1) (1) (0) (1) (0) (1) (1) (0) (1) (0) (1) (0) (1) (0) (1) (0) (0) (0) divide-by-4 slip synchronization 5 (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (3) (0) (1) (2) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) t ho t suv t ho t suv d 2 2 / ! ??4[ y+ n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d ______________________________________________________________________________________ 27 sync sync 2x input clk 4x input clk 1x divided clk (state) 1x divided clk (state) t suv = set-up time for valid clock edge. t ho = hold-off time for invalid clock edge. divide-by-2 edge synchronization t ho t suv t ho t suv 1234 1234 (1) (0) (1) (0) (1) (0) (1) (0) (1) (1) (0) (1) (0) force to 0 force to 0 (1) (0) (1) (0) (1) (0) (1) (0) (1) (0) (1) (0) (0) divide-by-4 edge synchronization 5 (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (1) (2) (3) (0) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (3) (0) (1) (2) d 2 3 / ! ?4[ y+ n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d 28 ______________________________________________________________________________________ k r n b y 2 : 6 1 8 ?? w d n p t - ?| - k ?# ?@ > y+ ? g p s n b ur?|??$ ?? ??w i t ? ? ik ?r ) e 1 ` C e 8 ` * p v u t f mr ?? ? tw# ?+ ? ? t q j { >??r ? +| ??g??l r ?+ @ ) 1 2 i * t q j { > ?? v| e 1 ` C e 8 `?|?? (6?2 m t c ? e 8 `?? n t c? e 1 `?? p w e e??r ?1 -? 2 / 9 w? 4 / 4 w? .?? p w e ek r| r? -? 6 1 ? 4 1 1 ? .?? ? d i `k ?r { <? @ ) 1 5 i [ 1 6 i *?? ? #|r? - k ? ? n b y 2 : 6 1 8 - k ? ? <? ? ?r? ? - x; ?|g ?s ? -0 - ? g~ .|k ?r?$ v b e dv ?k ? ? <?g s| ??l - 5- 6 ? ?s < ?| ??????by?? ? ???? k ? ?s??|l0?l d 2 4 [d 2 5 y?g h z?2 ?2e?]?|k ??##? e u j n f [ e m z ` i b m g ` u| 2 5? -?|*ak ? ?0# t- ????|k ? ???@ n b y 2 : 6 1 8 ! 2 4 1 n t q t b e d| ?? ?s ? ??|k ??2e - 7 [- 8 ?y4g h|n @ ??? zkn @ ???|*ak ? ?vg h| ?d 2 6 [d 2 7?, i e b ` c z q b t t > 2 e d m l u j n f?????? t ?? e u j n f|????- 9?, ?? t i e or? )[ m 8 *? <??@ y ?? ?? .| $ ?? @ ) 1 1 i *?c ? ???? |? ??? t i e o > 2 ? n b y 2 : 6 1 8 t i e o > 1 ) ?r] ?+ y+?? ?@yg?' t i e o r?? y t i e o ? \?? h ? - r?|? ? v|t j0 -?? @ ) 1 1 i *# ? a| b e d0x?? <? h ? [w ? y ?? ? r y+w ? y+ ?e [4 9 ? p? 5? ?i ?+??z p ?s hw ? y+j ] | ?g s???i2?z4 9 ? p ???-w ? y+ ?s|?o .? 2 6 t ? y + ? ? 6??1 ??g| ?e? 5j ??? 5 s i h ? ?? ? +?1 ??i? ? r j| ?? 5$ |?? ? - ? y+ ?s|?o .? 6 n ts ? s f g j p| s d .?k data timing control description da_bypass data aligner bypass. when this control is active (high), data and dclk delay is reduced by approximately 3.4ns (relative to da_bypass = 0). dly_half_t when this control is active, data output is delayed by half clock period (t/2). this control does not delay data output if mux mode is active. dtime<2:0> allows adjustment of data output delay in t/16 increments, where t is the sample clock period. dclktime<2:0> provides adjustment of dclk delay in t/16 increments, where t is the sample clock period. when dtime and dclktime are adjusted to the same setting, the rising edge of dclk occurs t/8 prior to data transitions. - 5 / ! k ? ? <? data timing control default description da_bypass 0 data aligner active dly_half_t 1 t/2 delay (3.85ns at 130msps) dtime<2:0> 101 -t/16 (0.48ns at 130msps) dclktime<2:0> 101 -t/16 (0.48ns at 130msps) - 6 / ! k ? ? <? ???? n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d ______________________________________________________________________________________ 29 d 2 6 / ! n @k ? ? ) w p w e e > ! 2 / 9 w * recommended data timing vs. sample rate max19507 fig15 sampling rate (msps) data delay (t fractional period) 120 110 100 90 80 0.5 1.0 1.5 2.0 0 70 130 v ovdd = 1.8v da_bypass = 1 +11/16 +10/16 +9/16 +8/16 +7/16 +6/16 +3/16 +2/16 +1/16 0 -1/16 -2/16 -3/16 +5/16 d 2 7 / ! n @k ? ? ) w p w e e > ! 4 / 4 w * recommended data timing vs. sample rate max19507 fig16 sampling rate (msps) data delay (t fractional period) 120 110 100 90 80 0.5 1.0 1.5 2.0 0 70 130 v ovdd = 3.3v da_bypass = 1 +11/16 +10/16 +9/16 +8/16 +7/16 +6/16 +3/16 +2/16 +1/16 0 -1/16 -2/16 -3/16 +5/16 sampling rate (msps) v ovdd = 1.8v from to da_bypass dly_half_t dtime<2:0> dclktime<2:0> 65 68 1 0 101 101 68 80 1 0 110 110 80 92 1 0 111 111 92 115 1 1 011 011 115 127 1 1 010 010 127 130 1 1 001 001 - 7 / ! n @ ?s ) w p w e e > ! 2 / 9 w * d 2 4 / ! ??k ? ? ) w p w e e > ! 2 / 9 w * factory-default nominal data timing vs. sample rate max19507 fig13 sampling rate (msps) data delay (t fractional period) 120 110 100 90 80 0.5 1.0 1.5 2.0 0 70 130 v ovdd = 1.8v da_bypass = 0 +11/16 +10/16 +9/16 +8/16 +7/16 +6/16 +3/16 +2/16 +1/16 0 -1/16 -2/16 -3/16 +5/16 d 2 5 / ! ??k ? ? ) w p w e e > ! 4 / 4 w * factory-default nominal data timing vs. sample rate max19507 fig14 sampling rate (msps) data delay (t fractional period) 120 110 100 90 80 0.5 1.0 1.5 2.0 0 70 130 v ovdd = 3.3v da_bypass = 0 +11/16 +10/16 +9/16 +8/16 +7/16 +6/16 +3/16 +2/16 +1/16 0 -1/16 -2/16 -3/16 +5/16 n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d 30 ______________________________________________________________________________________ ??1 ? n b y 2 : 6 1 8? y ?? ) b w e e *? ? ? 6?#v? 1?d 2 8?,i b w e e?|?1?? 3 w ?1 ??l 5 yf y ? 5?j]?? ?? + b w e e?1 ? 3 w ?l 5'?1 ? y+?1 ? y+] yf y ? 5? ? | 2 / 9 w???1 ?? 3 / 4 w? 4 / 6 w ! b w e er??1 *? ? 2 / 9 wr?1????? ? ? ?1 *?? q??2 y ? 5| ? r?+| r??1?u ?? [ ?? ? - @| ???? ??@? ; 5@ h?? ?zkk?? u <? @ ?w+ ? b w e e?? [ r? ?g s? ? ? b w e e ???? s? @k? b w e e ??|4 @ -2 ???? ? - @ s? ???? ? ?0 - > ?|? h ? t0 - spen [ t i e or?|n h <? ? -? ??w+ ? ? . b e d ?2e?u? 2 4 1 n t q t ? 7 6 t - : ?? 1 ?r ? ? sampling rate (msps) v ovdd = 3.3v from to da_bypass dly_half_t dtime<2:0> dclktime<2:0> 65 73 1 0 000 000 73 88 1 0 101 101 88 103 1 0 110 110 103 118 1 0 111 111 118 130 1 1 011 011 - 8 / ! n @ ?s ) w p w e e > ! 4 / 4 w * dtime<2:0> allowed dclktime<2:0> settings 111 (-3t/16) 111 (-3t/16) 110 (-2t/16) 110 (-2t/16); 111 (-3t/16) 101 (-1t/16) 101 (-1t/16); 110 (-2t/16); 111 (-3t/16) 000 (nominal) 000 (nominal); 101 (-1t/16); 110 (-2t/16); 111 (-3t/16) 001 (+1t/16) 001 (+1t/16); 000 (nominal); 101 (-1t/16); 110 (-2t/16); 111 (-3t/16) 010 (+2t/16) 010 (+2t/16); 001 (+1t/16); 000 (nominal); 101 (-1t/16); 110 (-2t/16); 111 (-3t/16) 011 (+3t/16) 011 (+3t/16); 010 (+2t/16); 001 (+1t/16); 000 (nominal); 101 (-1t/16); 110 (-2t/16); 111 (-3t/16) - 9 / ! e b ` c z q b t t ! > ! 2 e d m l u j n f [ e u j n f???|?? reset mode description power-on reset upon power-up (avdd supply voltage and clock signal applied), the por (power-on-reset) circuit initiates a register reset. software reset write data 5ah to address 0ah to initiate register reset. hardware reset a register reset is initiated by the falling edge on the shdn pin when spen is high. - : / ! ?? 1 n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d ______________________________________________________________________________________ 31 ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` bg? y r? $1 ? ]? j y r? n b y 2 : 6 1 8g]? jr?g s ????]r?q ?| t g e s [ u i e? jr? y+?? y 5r?53 p|t(uf w? j]r? y+$ ? b e dr???|g s? m s g$1 )d 2 9 *? s]g st ?]? jg s ? ? q| ? 1? s$1|f?? {? d n ` a y?1d|$1 ?? 2 ; 2 / 5| -2? y4| 1$12 ]?q?gr?q?g s ? m| ]??e? ??s^d 2 9?,|?? `?? h ) g d m l 0 3 *2|r? -2 w q| ?+v d 2 8 / ! ??1 ? in 2.3v to 3.5v enable out 1.8v regulator reference internal analog circuits avdd (pins 1, 12, 13, 48) gnd d 2 : / ! r?? h - `?? h |$1 ? ]r?q? 1 5 3 6 2 4 n.c. v in 0.1 f t1 mini-circuits adt1-1wt in_+ cm_ in_- n.c. 1 5 3 6 2 4 n.c. t2 mini-circuits adt1-1wt n.c. 0.1 f max19507 d 2 9 / ! r?? h? `?? h2 |$1 ? ]r?q? max19507 1 5 3 6 2 4 n.c. n.c. v in 0.1 f t1 mini-circuits adt1-1wt 36.5 0.5% 36.5 0.5% 0.1 f in_+ cm_ in_- n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d 32 ______________________________________________________________________________________ d 2 :?,? 5 - s]r?g st ?]? jg sd 2 :? ? $1?e? ?? a y4??*8 ? ? `?? h| ?r?g s 8 6 [ 2 2 1 {? ?g s? ?i| 6 1 {? {? {? d n ` 8i|r? a y?1 ] c ? ]r?g s d 3 1?,?] c ? ]r? n b y 5 2 1 9 ?? q r? ?^v?zr?g s|rsv0 -] 3 l ? ???1+ur? ??g??l a y @ 1 9 i ? ? ]r? n b y 2 : 6 1 8 w q| a y?1 *? ) 1 / 5 w? 2 / 5 w *' ? g? ? ]g s?i? a y?1?? 1 / 5 w? 2 / 5 w ? . ?r? d 3 2?,?]?? j| ?r?t ? 5 ` ` ` ` ` ` ` ` ` {?l 5 [? 5?z ?@02 n b y 2 : 6 1 8?g ? 5?z c s??l 5? ? ? # h 9?" q b e d ?4?g- #? h' ? ]?"c ? 1 / 2 g|?#?? s b w e e p w e e s f g j p d n b [ d n cl 5? h o er? ?? [???|??? 5? ?"mt??zg s| rsv' ?0x| k g s[#e - e | y [#?i? y r?[# |t 0x ? - '0x .w ]?"??z??g s# -a@ & ?? : 1 t o ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ?c j ;#v ) j o m * j o m?#?r =k" ]?#|??"m??? c? j o m ? j ;#v ) e o m * e o m5# r =k|[? qt 2 m t c /??? c? 2 ! m t c| e o m??zy ? i@ -i?r =k]?r =k| ? [?? ? e o m??"m ???c? e o m ? ?-,# r =k /r =k?|?|? |t /= z|?"$?|?2? 1 / 6 m t c ?5#?||?"$? /|?"$? .|?? d? d?-,? ?| x ?r? *?#?r = ks h /r =ks h|?|td??c? #?r =k|$?? j-, d 3 1 / ! ] c ? ]r?q? max19507 0.1 f 100 100 0.1 f in_+ cm_ 0.1 f in_- max4108 v in d 3 2 / ! ]?? j ?r? max19507 49.9 49.9 0.01 f 0.1 f 0.01 f clk+ clk- clkin n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d ______________________________________________________________________________________ 33 cg s? ) t t o g * t t o g?cg sr?? `??r| ? [^ ? h ? ]? ?z?t cg s?c? m?c? . 4 6 e c g t|]rg s ?lkt : ?t |z [ ? ? ? {c0x| k ?z [ ? ? ??|.g?? l d i j o b / n b y j n . j d / d p n ?|b g ) t o s * -k g|? p" fp y? t o s"m?5 x ? y r? ) s n t? * s n t ? ?? )?? *? / = z y 0kt |"c y? ?? ? ??? @&? {? b e d| j& h ) o? * ?? snr [max] = 6.02 x n + 1.76 # ? ? ? ? j ? ? ) ??z ?e ??? * t o sg s n tg s s n t ? v s n t t j ?f (uf ) i e 3 C i e 8 *? 2j `?? h|???? j g s , ! ^ ) t j o b e * t j o b eg s n tg s s n t , s n t ^? v s n t t j ?f (uf ) i e 3 C i e 8 * [? 2j `?? h|???? j s n t^t j (uf ) i e 3 C i e 8 * ]r?2?? *? ) t g e s 2 [ t g e s 3 * t g e s5 ?f )"mg s? j *| s n t m?yt j? |? m2? j| s n t m??2 j??]? t g e s 2 (o ??"? 3( t 4(uf^|2v t g e s 3? c?yt j 3( 4(uf ? |"?2 j ? uf^ ) u i e * u i e0?5r?g s (uf| s n t? [ ?f? -2+-,? | w 2 ? ?f m? w 3 C w 8 ? 3(? 8(uf ) i e 3 C i e 8 *| m? c ) j n 4 * j n 4? `??r c| ? h y 5]rr? g j o 2 [ g j o 3 ? h|? ? 5r?g s?3? . 8 e c g t c j ??? 3 ! y ! g j o 2 . ! g j o 3 3 ! y ! g j o 3 . ! g j o 2 3 ! y ! g j o 2 , ! g j o 3 3 ! y ! g j o 3 , ! g j o 2 ; ?? r?g s?g ?|? ? ?rg ; ? ) u b e *5 ?g ?? ?# g~ .|?c ; ?? ; ?? ) u b k *?c?gg? . ; ? |$ ? -q? a ? . -q? a ? .5 b e d- - x ?"?|r?~? ? r a ???| . ? -q? a ? .?r? x ? 2 1 &|= z ?r? ? ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` `g? process: cmos thd vvvvvv v log = +++++ ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 6 2 7 2 1 sinad noise distortion signal rms rms rms log = + ? ? ? ? ? ? ? ? 20 22 snr signal noise rms rms log = ? ? ? ? ? ? 20 n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d top view max19507 13 14 15 16 17 18 19 20 21 22 23 24 avdd sync clk+ clk- gnd gnd dorb dclkb i.c. i.c. d0b d1b 48 47 46 45 44 43 42 41 40 39 38 37 1 2 345678910 11 12 avdd cs/outsel sclk/div sdin/format dclka dora d7a d6a d5a d4a d3a d2a avdd cmb inb- inb+ i.c. shdn refio spen ina- ina+ cma avdd 36 35 34 33 32 31 30 29 28 27 26 25 ovdd d2b d3b d4b d5b d6b d7b i.c. i.c. d0a d1a ovdd + *ep *exposed pad ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` [ m|? 34 ______________________________________________________________________________________ ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` v?g? ??" | v?jpg? [ fdz ?? china.maxim-ic.com/packages ??@ v? i|| , $ t . ?-, s p i t? v?d| -t :y4|?? oc v?d? v?? s p i t?? v? o v? i jp s fdz s 48 tqfn-ep t4877+4 21-0144 90-0130 n b y 2 : 6 1 8 w0x 9? 2 4 1 n t q t ! b e d n b y j ny n b y j n?-2j|? \? 5' ? y ?? - n b y j n? ?? \ . ??? \0| ? ??- t ? [ ?|z ? maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ______________________ 35 ? 2010 maxim integrated products n b y j n 5 n b y j n ! j o u f h s b u f e ! q s p e v d u t - ! j o d / |?* 0 10/08 1 9/10 5, 6, 28, 29, 30 ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ?? ?% ?? s ???e ? ? ? "?t n b y j n ? ?0 ? 9 4 3 9g( ?v i 2 1 1 1 9 4 ? e? ?? 9 1 1 ! 9 2 1 ! 1 4 2 1 ? ?? 1 2 1 . 7 3 2 2 6 2 : : ^? 1 2 1 . 7 3 2 2 6 3 : : ? ? d n p trq?|$ ? ?d ? .vlk |
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